1. Field of the Disclosure
The disclosure is related to a non-volatile semiconductor memory device, and more particularly to an NAND (Not And) flash memory.
2. Description of Related Art
An NAND flash memory is formed to have a memory block array. The memory block array is formed with a plurality of NAND strings arranged in a column direction. The NAND string is formed to have a plurality of memory cells connected in series and a selecting transistor connected to both ends thereof, wherein an end portion is connected to a bit line via a bit line side selecting transistor and the other end portion is connected to a source line via a source line side selecting transistor. The operation of reading out or programming (writing in) data is performed through the bit line that is connected to the NAND string.
FIG. 1 is a structural view illustrating a bit line selecting circuit of a conventional NAND flash memory. Here, the drawing shows a pair of bit lines, namely an even bit line BLe and an odd bit line BLo. A bit line selecting circuit 10 includes a first selecting portion 20 including a bit line selecting transistor BLC. The bit line selecting transistor BLC connects the even bit line BLe or the odd bit line BLo to a read-out circuit. A second selecting portion 30 includes an even bias voltage transistor BIASe and an odd bias voltage transistor BIASo, an even bit line selecting transistor BLSe and an odd bit line selecting transistor BLSo. The even bias voltage transistor BIASe and the odd bias voltage transistor BIASo apply a bias voltage VPRE to the even bit line BLe and the odd bit line BLo. The even bit line selecting transistor BLSe connects the even bit line BLe to the bit line selecting transistor BLS. The odd bit line selecting transistor BLSo connects the odd bit line BLo to the bit line selecting transistor BLC. The bit line selecting circuit 10 is connected to the read-out circuit 40. Here, the second selecting portion 30 is formed on a P substrate that is different from a P well region that forms a grid array. When an erase operation is performed, an erase voltage is applied to a selected block (P well) so that all the bit lines are boosted to the erase voltage. On the other hand, since the P substrate is 0 V (GND), the even bias voltage transistor BIASe and the odd bias voltage transistor BIASo, the even bit line selecting transistor BLSe and the odd bit line selecting transistor BLSo that form that the second selecting portion 30 include a high voltage (HV) transistor that has a thick gate oxide film, long gate length and bears the high voltage.
In Japanese Patent No. 5550609, Japanese Patent Publication No. JP 2011-23661 and non-patent literature (K. Fukuda. Et al., “A 151 mm2 64 Gb MLC NAND Memory in 24n, CMOS Technology”, IEEE International Solid-State Circuit Conference, Digest of Technical Paper P198-199, Session 11, 2011), as shown by FIG. 2, the second selecting portion 30A of a bit line selecting circuit 10A includes a low voltage (LV) transistor. A relay portion 32 that includes a high voltage transistor BLS is configured between the second selecting portion 30A and the first selecting portion 20. The transistors BIASe, BIASo, BLSe, BLSo that form the second selecting portion 30A are formed in a block 50, i.e. P well 6, that forms the memory array of the NAND string unit NU. The transistors BIASe, BIASo, BLSe and BLSo are low voltage transistors that have short gate length and thin gate oxide film and formed in the same manufacturing process in which the memory cell is manufactured. The transistor BLS of the relay portion 32 is configured at an external side of the P well 60 that forms the memory cell array so that the transistor BLC of the first selection portion 20 is separated from the transistor of the second selecting portion 30A. The second selecting portion 30A is set as a structure of a low voltage transistor so as to reduce the arrangement area used for the second selecting portion 30A, whereby implementing minimizing the size of the overall memory. Moreover, when the erase operation is performed, about 20 V of an erase voltage or an erase pulse is applied to the P well 60. At this time, the gate of all transistors that form the second selecting portion 30A is set to be in a floating state. The gate of the transistor is coupled to the capacitor of the P well 60 and thus is boosted to be close to the erase voltage. Therefore, a big potential difference is not applied to the gate oxide film of the transistors BIASe, BIASo, BLSe, BLSo, thereby avoiding breakdown of the gate oxide film.